The invention relates generally to a processor adapted to be operable in a single-thread mode and a multi-thread mode and a method for operating a processor in a single-thread mode and a multi-thread mode.
In today's microprocessors, in particular server class processors, the capability to provide enhance processing performance in both a single-thread (ST) and a multi-thread (MT) environment becomes a significant differentiator in processor design. As processor architectures have moved to wider super-scalar configurations, it has proven to be a challenge to let multiple execution units operate on the same data in an ST setup (e.g., because of timing conflicts that may occur between the multiple execution units at the time an execution finishes).
Such a processor could have a single register file serving all execution units in the processor needed for operand data and result write-back. However, this drives the need for excessive amounts of read/write ports on such register files, which may cause a series of negative consequences like high power and physical space consumption.
There is also a trend towards more multi-threaded setups with 2, 4 and more threads within the same processor. The nature of multi-threading expands the choice for a processor's scheduling unit to select instructions to run on the execution units that cannot access data from all threads, but only from a particular set of threads. As the number of threads grows, the amount of registers a processor needs to handle exceeds physical and frequency constraints. Current architectures try to solve this problem by implementing multiple register files.